The new solutions combine Synopsys’ AI-powered EDA tools with Ansys golden signoff analysis, targeting critical bottlenecks in timing, design closure, and multi-die architectures. By shifting these physics-aware checks earlier in the cycle, engineering teams can reduce iterations and improve power, performance, and area (PPA) metrics. The portfolio leverages GPU-accelerated flows, utilizing NVIDIA CUDA-X libraries to enhance simulation speeds, with some workflows reporting up to 10x faster design closure.

Industry leaders, including NVIDIA, Samsung Foundry, MediaTek, and Cisco, have already begun integrating the technology. NVIDIA reported that the use of cuDSS libraries has provided up to 13x acceleration for complex simulations. Similarly, Samsung Foundry is utilizing the platform to incorporate IR drop and thermal stress effects directly into timing signoff to recover margins. As chip complexity rises, the platform seeks to provide a "correct-by-construction" methodology for designers navigating the transition toward sophisticated multi-die and photonic systems.